Machine Learning Enabled Root Cause Analysis For Low Power Verification

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Next-generation SoCs with advanced graphics, computing and artificial intelligence capabilities are posing unforeseen challenges in verification. Designers and verification engineers using static verification technologies for low power often see many violations in the initial stages. Efficient debugging and determining root cause is a real issue and a big challenge when violation counts are huge. This article explores deterministic and machine-learning techniques to identify the root cause for a related group of violations. These techniques significantly help to reduce the overall turnaround time for verification signoff to “shift-left” and ensure that bugs do not escape into silicon.

Design complexities are continuing to grow exponentially, resulting in an increase in the violations report volumes from 10K – 1M violations, depending on the design. Manual debug of these violations is a challenge and is also time-consuming requiring expertise and domain knowledge. The goal of this technology is to reduce the debug turnaround time by creating groups and identifing root cause to the user so that debug time can be saved. This technology uses unsupervised (clustering) machine learning to first group related issues/violations and then find the relations between effect violations and cause violations.

There are likely different root cause scenarios for low power designs, like Power State Table issues, UPF issues, supply driven Isolation/Level Shifter issues, rail order checks, etc. The effect of these issues can be broadly categorized into strategy related violations like missing or redundant strategies. This flow creates the needed information in the tool to group related violations into clusters. The user then needs to mainly focus on debugging these violation clusters rather than debugging individual violations one by one. The figure below illustrates this.

Figure 2: Violation report used for root cause analysis

The results seen on different designs using this technique are highly encouraging. The coverage of clusters on some designs is as high as 99%. The figure below showcases the results on some designs.

Machine learning enabled root cause analysis is enabling both design and verification engineers to boost their verification productivity, ensuring a “shift-left” in the verification turnaround time.

Susantha Wijesekara is an applications engineering manager at Synopsys focused on low power products. Previously, he was a senior verification engineer at Atrenta.